As integrated circuit devices become more highly integrated, source and drain regions may more often be formed in shallow junction regions to stabilize the characteristics of transistor. Furthermore, a contact with low resistance may be formed on the source and drain regions to facilitate high-speed operation of the transistor.
Conventional processes for forming source/drain regions in shallow junctions may include forming a source/drain region that does not extend deep into the substrate and raising the height of the source/drain region by forming a silicon epitaxial layer on the shallow source/drain region using a selective epitaxial layer growth (SEG) method. Furthermore, conventional processes for forming a source/drain region with low resistance may include depositing a metal such as Titanium (Ti), Cobalt (Co) and/or Nickel (Ni) on the source/drain regions, performing a solid-state reaction and forming a low-resistant silicide layer.
Conventional methods of fabricating integrated circuit devices using an SEG method and a silicide layer as described above will be described further below with respect to FIGS. 1 through 3. FIGS. 1 through 3 are cross sectional views illustrating processing steps in the fabrication of conventional integrated circuit devices. As illustrated in FIG. 1, a gate stack pattern 20 is formed on an integrated circuit substrate 10. The gate stack pattern 20 includes a gate insulating layer 12, gate electrodes 14 and 16, and a capping layer 18. The gate insulating layer 12 includes, for example, an oxide, and the gate electrodes 14 and 16 include, for example, polysilicon and tungsten silicide. The capping layer 18 includes, for example, nitride.
A low-concentration impurity region 22 is formed on the integrated circuit substrate 10 to be aligned with the gate stack pattern 20. Gate spacers 24 are formed on both sidewalls of the gate stack pattern 20. The gate spacers 24 are formed by anisotropically etching a nitride layer that is formed on the surface of the integrated circuit substrate 10.
A high-concentration impurity region 26 is formed on the integrated circuit substrate 10 to be aligned with the gate spacers 24. Consequently, the source/drain region includes both the low-concentration impurity region 22 and the high-concentration impurity region 26. A silicon epitaxial layer 28 is formed on the high-concentration impurity region 26 of the source/drain region using the SEG method. Generally, use of the SEG method generates a facet 30 in which the silicon epitaxial layer 28 grows thinner than other parts in the junction.
As illustrated in FIG. 2, a metal layer 32 is formed on the surface of the integrated circuit substrate 10 having the gate spacers 24 and the silicon epitaxial layer 28. In other words, the metal layer 32 is formed on the gate spacers 24, the silicon epitaxial layer 28, and the capping layer 18. The metal layer 32 is formed of a metal, such as Ti, Co, Ni, or the like.
As illustrated in FIG. 3, a silicidation process is performed in which the silicon epitaxial layer 28 and the metal layer 32 are thermally treated. Through this process, the silicon epitaxial layer 28 formed on the high-concentration impurity region 26 becomes a silicide layer 34, but the metal layer 32 formed on the capping layer 18 and the gate spacers 24 does not turn into a silicide layer. The metal layer 32 is removed by performing a wet etch.
According to the methods of fabricating conventional integrated circuit devices described with respect to FIGS. 1 through 3, the silicon epitaxial layer 28 grown by the SEG method on the high-concentration impurity region 26 does not typically have a uniform thickness over the high-concentration impurity region 26 due to the facet 30 in the regions adjacent to the gate spacers 24. Accordingly, the silicide layer may be formed close to the edge of the high-concentration impurity region and extend too far into the high-concentration impurity region/substrate under a thinner portion of silicon epitaxial layer 28 near the edge area of the source/drain region. This may cause the device to exhibit weak junction leakage current characteristics because, for example, the silicide layer penetrates too far into the substrate 10 and the silicide junction (36 of FIG. 3) may not be uniform.